1. Field of the Invention
The present invention relates to a data transmission technique, and particularly to a technique for transmitting data at high speed.
2. Description of the Related Art
Conventional high-speed inter-LSI data transmission systems include source synchronous signaling. In the source synchronous signaling, a transmitter end LSI sends data and clock at the same time, and a receiver end LSI delays the phase of a received clock in accordance with the received data and uses the delayed phase for transmitted data reading.
A clock-step execution function is debug means of an LSI system consisting of plural LSIs that are operated at a single reference clock. The clock-step execution function to check state transition of each unit while running the clock cycle one by one, and the function enables a detailed search of system operations. In order to support the clock-step execution function, a mechanism to prevent data loss during the data transmission between LSIs is required.
An example of the data transmission system employing the source synchronous clocking is shown in FIG. 1.
In FIG. 1, an internal clock (CLK) of a transmitter end LSI 100 is transmitted through a clock buffer 101 and to a receiver end LSI 200 by an IO buffer 102.
Meanwhile, the internal clock of the transmitter end LSI 100 is also input to a clock chopper 111. The clock chopper 111 normally outputs an H-level (high level) signal but outputs a chopper signal (an L-level (low level) short time signal) when one edge (e.g. falling edge) of the internal clock is detected. The output signal of the clock chopper 111 is input to each of clock terminals that are D-latches 112-1, . . . , 112-m, 113-1, . . . , 113-m. 
Transmission data that is m-bit parallel data is input bit by bit basis to the D-latches 112-1, . . . , 112-m. The outputs of the D-latches 112-1, . . . , 112-m are input to the D-latches 113-1, . . . , 113-m, respectively. Consequently, transmission data with internal clock that is one cycle before the internal clock in the D-latches 112-1, . . . , 112-m is latched in the D-latch 113-1, . . . , 113-m. The transmission data output from the D-latch 113-1, . . . , 113-m is transmitted to the received end LSI 200 by IO buffers 114-1, . . . , 114-m. 
It should be noted that a gated stop signal is input to the clock buffer 101 and the clock chopper 111. The clock buffer 101 stops outputting a clock when the gated stop signal is changed to the H-level signal. The clock chopper 111 stops the chopper signal and continues to output the H-level signal when the gated stop signal is changed to the H-level signal.
In the receiver end LSI 200, the transmission clock transmitted from the IO buffer 102 of the transmitter end LSI 100 is received by an IO buffer 201, and is transmitted to a phase adjuster unit 202. The phase adjuster unit 202 delays the transmission clock. The amount of delay at that time is determined in consideration of wiring between the transmitter end LSI 100 and the receiver end LSI 200, wiring in the LSI, and an amount of delay due to variation in process of the LSI. The transmission clock output from the phase adjuster unit 202 is input to the clock chopper 203.
Meanwhile, the transmission data transmitted from the IO buffers 114-1, . . . , 114-m of the transmitter end LSI 100 is received by the IO buffers 211-1, . . . , 211-m of the receiver end LSI 200 and is input to D-latches 212-1, . . . , 212-m. The D-latches 212-1, . . . , 212-m output the transmission data when a chopper signal is input to each clock terminal from a clock chopper 203.
The transmission data output from the D-latches 212-1, . . . , 212-m is transmitted to FIFO circuits 213-1, . . . , 213-m. The FIFO circuits 213-1, . . . , 213-m form a ring buffer with generation of pointers in a write pointer generation unit 204 and a read pointer generation unit 222. The ring buffer is used for switching the clock of the transmission data from the transmission clock (i.e. the internal clock of the transmitter end LSU 100) to the internal clock of the receiver end LSI 200.
The write pointer generation unit 204 generates a write pointer indicating any one of plural buffers of the FIFO circuits 213-1, . . . , 213-m, and switches the write pointer so that the other buffers are indicated successively based on the chopper signal from the clock chopper 203. On the other hand, the read pointer generation unit 222 generates a read pointer indicating any one of plural buffers of the FIFPO circuits 213-1, . . . , 213-m, and switches the read pointer so that the other buffers are indicated successively based on the chopper signal from the clock chopper 221. Note that the internal clock of the receiver end LSI 200 is input to the clock chopper 221.
Of the plural buffers of the FIFO circuits 213-1, . . . , 213-m, the transmission data output from the D-latches 212-1, . . . , 212-m is written in the one indicated by the write pointer generated by the write pointer generation unit 204, and is read out from the one indicated by the read pointer generated by the read pointer generation unit 222. In such a manner, the clock of the transmission data is made the switch from the internal clock of the transmitter end LSI 100 to the internal clock of the receiver end LSI 200.
The transmission data output from the FIFO circuits 213-1, . . . , 213-m is, after being latched once in the D-latches 214-1, . . . , 214-m, transmitted into the received end LSI 200 in accordance with the chopper signal from the clock chopper 221.
It should be noted that the clock chopper 221 in the receiver end LSI 200 has an input of a gated stop signal that is the same as the one in the transmitter end LSI 100. The clock chopper 221 stops the chopper signal and continues to output the H-level signal when the gated stop signal is changed to the H-level signal.
Operations of a case that the clock-step execution function is executed in the circuit shown in FIG. 1 are explained.
The transmission data transmitted from the transmitter end LSI 100 is retrieved by the D-latches 212-1, . . . , 212-m in the initial stage of the receiver end LSI 200 at the transmitter end internal clock that has the same cycle as the one in the D-latches 113-1, . . . , 113-m in the last stage of the transmitter end LSI 100. Consequently, even if the gated stop signal is changed to the H-level signal and the transmission clock is stopped, all of the transmission data transmitted from the transmitter end LSI 100 can be received by the receiver end LSI 200. Because the transmission clock transmitted from the transmitter end LSI 100 stops at the completion of the transmission data reception in the receiver end LSI 200, overwriting of the transmission data would not occur in the ring buffer (FIFO circuits 213-1, . . . , 213-m) afterward.
FIG. 2 shows an example of a time diagram of each unit in the transmission system shown in FIG. 1.
The correspondence relationship between each chart of FIG. 2 and FIG. 1 is indicated by numbers in parenthesis. Note that a chart (0) in FIG. 2 is not shown in FIG. 1. This chart indicates an output waveform of the clock chopper 111 of the transmitter end LSI 100 when the gated stop signal is ignored. A chart (11) in FIG. 2 indicates data storage state in each of the plural (in this case 16) buffers in the ring buffer 213-1.
In FIG. 2, a solid line arrow indicates that the chopper signal from the clock chopper 203 stops (see chart (8)) with a delay from stop of the transmission clock (see chart (5)) by the gated stop signal (see chart (2)). In this case, 2.5 cycle delay is generated between the stop time of the transmission clock in the chart (5) and the stop time of the transmission clock in the chart (6). This is the amount of delay generated in the clock transmission from the transmitter end LSI 100 to the receiver end LSI 200 in the example of the charts. 0.5 cycle delay is generated between transmission clock shown in the chart (6) and the chopper signal from the clock chopper 203 shown in the chart (8). This is an amount of adjustment delay in the phase adjuster unit 202 of the example of the charts.
A broken line arrow shown in FIG. 2 is discussed. The D-latch 113-1 in the last stage of the transmitter end LSI 100 stops at a state in which data “DT7” is output as shown in the chart (4) by means of the gated stop signal shown in the chart (2). The data “DT7” is delayed in the data transmission from the transmitter end LSI 100 to the receiver end LSI 200. However, the original data “DT7” can be received as shown in the chart (9) because the D-latch 212-1 in the initial stage of the receiver end LSI 200 is operated in accordance with the transmission clock transmitted from the transmitter end LSI 100 in the configuration of FIG. 1. In this configuration, additionally, switching of the write pointer by the write pointer generation unit 204 is also operated in accordance with the transmission clock transmitted from the transmitter end LSI 100. As a result, the data “DT7” output from the D-latch 212-1 can be stored in a proper buffer of the FIFO circuit 213-1 as shown in the chart (11).
In the source synchronous clocking described above, each bit data is latched at the same transmission clock when the parallel data is received. For that reason, as shown in FIG. 3A, in order to secure set-up time and hold time for every bit, variation in the amount of delay among bits in the data transmission has to be sufficiently smaller than the cycle of the transmission clock. If the variation in the amount of delay is larger than the cycle of the transmission clock, bits in which the set-up time and hold time cannot be secured may be generated as shown in FIG. 3B. In other words, the source synchronous signaling has limitations in high throughput data transmission.
In order to overcome the above problem, a data synchronous transmission system for adjusting the phase of the transmission clock at data edge for each bit is proposed as a system in which set-up time and hold time can be secured even if the delay variation in bits exceeds the cycle of the transmission clock. Note that the system adjust the phase at the data edge, the receiver end clock can be used instead of the transmitter end clock.
In relation to the technologies explained above, Japanese Patent Application Publication No. 2006-5665, for example, discloses a technology for improving the gap between a received data signal and a received clock signal that is delayed by adjusting the amount of delay of the received clock signal based on the detection result of the relationship between phases of the two signals.
As another example, Japanese Patent Application Publication No. 2006-19790 discloses a technology for absorbing a phase difference generated between bits at the time of high-speed transmission of parallel data by a ring buffer.
In addition, International Publication No. WO2004/031926, for example of a technology relating to the present invention, discloses a technology of the use of high frequency clock generated from a reference clock in each device so as to realize serial transmission of data between devices using different frequency clocks.
Japanese Patent Application Publication No. 2006-50102, for the other example, discloses a technology to control variation in transmission of each bit at the time of high-speed transmission of parallel data by the use of a reference signal shared by a transmitter device and a receiver device and a training pattern transmitted from the transmitter device to the receiver device.
In the above data synchronous signaling, the transmission clock used for latching the data in the initial stage at the receiver end can be more than 1 cycle off. For that reason, there is no assurance that the transmission clock is the same as the clock transmitted with the data from the transmitter end. In addition, because the phase of the clock used for latching the data of each bit is separately adjusted with respect to each bit of the parallel data, there is no assurance that the phase of each clock is the same as each other after the phase adjustment. For that reason, the way to correctly read the latched parallel data becomes a problem that has to be solved.
If the clock is stopped by application of the clock-step execution function, some bits of the parallel data can be received while other bits cannot be received due to the variation in transmission of bits, and as a result, there is no assurance that the data being transmitted can be received correctly.
Furthermore, even if an equalizer that stabilizes the waveform of the transmission clock during high-speed transmission is provided in the transmission path, because the waveform of the clocks at the start and at the stop cannot be assured by the equalizer, data transmission reliability cannot be assured when the clock-step execution function is executed.